The present invention relates to a semiconductor memory device, and more particularly to a data output circuit in a memory device formed as an integrated circuit device.
A semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of digit lines coupled with memory cells at the respective columns, a selection circuit responding to address signals and selecting one of the rows and one of columns to designate one memory cell, and a data output circuit detecting the potential on the selected digit line, which represents the data stored in the selected memory cell, and producing an output data of "0" or "1" which corresponds to the data stored in the selected memory cell.
The memory capacity of the memory device has been increased more and more in recent years, so that the number of memory cells coupled to each digit line is made large. Each digit line thereby becomes long to make the stray capacitance thereof large. As a result, a time constant for charging and discharging each digit line becomes large and the speed for producing the output data is made slow.
In order to enhance the data output speed, it is required to suppress the change in potential on each digit line responsive to the data stored in the selected memory cell and to detect such a relatively small potential change on each digit line. For this purpose, the data output circuit is composed of an inverting amplifier which is operatively connected to the selected digit line and which is provided with a feedback loop, a reference voltage generator generating a reference voltage, and a comparator comparing the output voltage of the amplifier with the reference voltage.
It will be assumed that the selected memory cell draws no current when its storing data is "0" and draws a predetermined current when its storing data is "1". The digit line is therefore charged by the inverting amplifier when the data stored in the selected memory cell is "0". Since the inverting amplifier is provided with the feedback loop, the digit line is charged up to such a level that the potential thereon becomes equal to the output potential of the inverting amplifier. The output potential of the amplifier in this case is indicated as a first output level. When the selected memory cell stores the data of "1", it discharges the digit line with the predetermined current. The potential on the digit line is thereby lowered, but the lowering of the digit line potential is suppressed by the feedback loop of the inverting amplifier. Since the potential on the digit line is lowered, the output potential of the inverting amplifier increases. The output potential at this time is determined by the current drawn by the selected memory cell, an impedance of the feedback loop and the potential at the digit line, and is indicated as a second output level.
The reference voltage generated by the generator is designed to take an approximately intermediate level between the first and second output levels of the inverting amplifier. Accordingly, the comparator produces the output data of "0" or "1" in response to the output level of the inverting amplifier.
Thus, the change in potential on the digit line responsive to the data stored in the selected memory cell is suppressed, and such a small potential change of the digit line appears as the amplified output level change of the inverting amplifier. Accordingly, the data stored in each memory cell is read out at a high speed.
As well known in the art, it is unavoidable that the memory cells in the integrated circuit memory device are actually formed with dimensions deviated from the designed values because of the change in the manufacturing condition, for example. As a result, the current actually drawn by each memory cell becomes larger than the designed value, or smaller than it. Since the second output level of the inverting amplifier is determined by the current drawn by the memory cell as described above, the difference between the second output level and the reference voltage becomes larger or smaller than the designed value. The comparator is generally composed of a differential amplifier, and therefore it requires a voltage difference above a predetermined value between its two input voltages in order to produce the output data of "1" or "0". The comparator produces an intermediate level between the data "1" and "0" if the difference between the second output level (high level) of the inverting amplifier and the reference voltage is smaller than the designed value due to the deviation of the current of each memory cell to a smaller value. On the other hand, if the difference between the second output level and the reference voltage is too large as compared with its designed value due to a large current drawn by each memory cell, the change in potential from the second level to the first level is broadened to deteriorate the speed for the data read operation.